An AI accelerator looks like a modest slab of metal and ceramic on a circuit board, but it is the end of one of the most intricate manufacturing chains humans have built. Understanding the stages, even at a high level, explains why chip supply is hard to expand quickly, why yields matter so much and why a design decision made years earlier shapes what you can buy today. This walkthrough follows a chip from concept to finished part.

Stage One: Design and Verification

Before any silicon is touched, engineers describe the chip in a hardware description language, simulate it extensively and translate it into a physical layout: billions of transistors and the wiring between them, arranged in many stacked layers. Verification is exhaustive because fixing a mistake after manufacturing starts is slow and costly.

Design teams usually rely on a foundry’s process design kit, a set of rules and models describing what that factory’s process can reliably build. Some companies design chips and send them to a separate foundry to manufacture; others do both in-house.

Stage Two: Making the Wafer

Chips are built on wafers, thin discs sliced from a highly purified single crystal of silicon. A single wafer carries many copies of the chip design, laid out in a grid.

Fabrication repeats a cycle of steps, many times over, to build up layers:

1. Deposition adds a thin film of material onto the wafer.
2. Photolithography coats the wafer with a light-sensitive layer and exposes it through a patterned mask, transferring the circuit pattern. This is the step that sets the finest feature sizes.
3. Etching removes material where the pattern directs, carving the structures.
4. Doping and implantation change the electrical properties of selected regions, forming transistors.
5. Cleaning and planarisation keep surfaces flat and free of contaminants between layers.

A modern chip may pass through hundreds of steps. Contamination at microscopic scale can ruin a die, which is why fabrication takes place in ultra-clean rooms.

Stage Three: Interconnect Layers

After transistors are formed, many layers of metal wiring connect them. These layers are built with the same deposit, pattern and etch logic, with insulating material between them. Wiring density and resistance affect speed and power, so interconnect is a major part of overall chip performance, not an afterthought.

Stage Four: Wafer Testing

Before the wafer is cut, probes contact each die to run electrical tests. Dies that fail are marked. The share of working dies on a wafer is the yield, and it depends on process maturity, die size and defect density. Larger dies are more likely to contain a defect, which is one reason very large AI processors are costly to produce and why some designs split into smaller pieces.

Stage Five: Dicing and Packaging

Good dies are cut from the wafer and placed in packages that provide electrical connections, mechanical protection and a path for heat to escape. For AI accelerators, packaging has become a performance feature in its own right, often combining the processor die with stacked memory and sometimes multiple compute dies on a shared substrate. Advanced packaging raises its own manufacturing complexity and capacity constraints.

Stage Six: Final Test and Binning

Packaged parts undergo further testing for function, speed and power. Chips from the same wafer often differ slightly in the clock speeds or power levels they achieve, so they may be sorted into grades. Some designs include spare or deliberately disabled sections so that a die with a minor defect can still be sold as a lower-tier part.

The Flow at a Glance

Stage	What happens	Why it matters for AI chips
Design and verification	Logic and layout are created and checked	Errors are very costly once manufacturing begins
Wafer fabrication	Layers are built through repeated process cycles	Process capability sets density, speed and power
Interconnect build	Metal wiring connects transistors	Affects performance and energy use
Wafer test	Each die is electrically probed	Determines yield and cost
Dicing and packaging	Dies are cut and assembled, often with memory	Packaging increasingly shapes final performance
Final test and binning	Parts are graded by function and speed	Explains product tiers from the same design

Why Capacity Is Slow to Add

Building a fabrication facility takes substantial time, specialised equipment with long delivery schedules and a skilled workforce. Tooling for the most advanced steps is made by a small number of suppliers. Even after construction, a new line needs time to ramp up and reach good yields. This is why shortages in chip supply do not resolve overnight, and why manufacturing and packaging capacity can be as limiting as chip design.

For current details on capacity, process offerings or schedules, consult manufacturers’ own published information, since such facts change.

A Short Hypothetical

Imagine a company designs a large AI processor. The first wafers reveal that a certain fraction of dies contain defects, and because the die is large, fewer good chips come from each wafer than hoped. The team responds in two ways. They refine the process and the design to improve yield, and they plan a later product that splits the processor into smaller dies connected inside one package. Neither fix is instant; each takes months of engineering. The story illustrates how manufacturing realities feed back into architecture.

Frequently Asked Questions

What is a foundry? A foundry is a company that manufactures chips designed by others. Many chip companies design products and outsource fabrication to a foundry.

What does a process node name mean? Historically it referred to a feature size. Today node names are largely marketing labels that indicate a generation of technology rather than a precise measurement, so compare by documented characteristics, not names alone.

Why does die size affect cost? A larger die occupies more of the wafer and has a greater chance of containing a defect, so fewer good chips are obtained per wafer.

Why is packaging suddenly in the news? AI processors depend on tightly integrated memory and sometimes multiple dies, so packaging capacity and technique have become important constraints.

How long does it take to make a chip? The fabrication of a wafer passes through very many steps and takes a substantial period; exact durations vary by process and facility.

Next Step

Choose one stage from the table, such as lithography or advanced packaging, and read a manufacturer’s own technical overview of it. Seeing how one stage works in detail makes the rest of the supply chain easier to follow.