Every chip on a wafer is a lottery ticket against tiny defects. Understanding yield, meaning the share of chips that come out working, explains a lot about why some AI processors are scarce, why prices behave as they do, and why designers keep reaching for chiplets.
What Yield Is
A wafer is a disc of silicon that carries many copies of a chip pattern, each copy called a die. After fabrication, each die is tested. Yield is the fraction that works well enough to sell. If a wafer carries a hundred dies and eighty pass, the yield is eighty percent. That figure is purely illustrative; real yields are company confidential and vary by product and process maturity.
Yield matters because the cost of processing a wafer is largely fixed. You pay roughly the same whether the dies on it are good or bad. Fewer good dies per wafer means each good die effectively carries more of the cost.
Why Defects Are Unavoidable
Chip features are extraordinarily small. A stray particle, a flaw in the silicon, or a slight variation in a patterning step can ruin the circuit where it lands. Manufacturers invest heavily in cleanliness and process control, yet some defects remain, scattered more or less randomly across the wafer.
Because defects are scattered, the chance that a given die contains at least one grows with the area of that die. This is the central relationship: bigger dies catch more defects.
Why Large AI Chips Are Hard
Many AI accelerators are large chips, because putting more compute and memory on one die avoids slower connections between dies. But large dies hit two penalties at once.
- Fewer dies fit on a wafer, and the unused wafer edge wastes more area.
- Each die is more likely to contain a defect.
Together these make the cost of a good large die rise faster than its area. A die twice the size is more than twice as expensive per good unit, and the gap widens as dies approach the limits of what the manufacturing equipment can pattern in one exposure.
Ways Designers Fight Back
Redundancy. Designers include spare units, such as extra compute blocks or memory rows, so that a defect in one can be bypassed. A die with a flaw in a spare-covered area can still be fully functional.
Binning. Dies that work but not perfectly are sorted into grades. A chip with a few disabled blocks or that cannot reach the top clock speed can be sold as a lower tier product. This salvages value from dies that would otherwise be scrap, and it is one reason a product family has several versions.
Chiplets. Instead of one large die, the design uses several smaller dies assembled together in a package. Smaller dies yield better individually, and manufacturers can test them first and combine only the good ones. The tradeoff is added packaging complexity and the need for fast links between dies.
Process maturity. Yields typically improve as a manufacturing process matures, since engineers find and fix sources of defects over time. Early production of a new process often has lower yield.
How the Pieces Compare
| Approach | How it helps yield | Cost or tradeoff |
|---|---|---|
| Redundancy | Lets dies with defects still work | Spends area on spare blocks |
| Binning | Sells partially working dies as lower grades | Creates multiple product tiers |
| Chiplets | Smaller dies, test before assembly | Packaging complexity, die-to-die links |
| Smaller die design | Fewer defects per die | Less on-chip integration |
| Process maturity | Fewer defects over time | Takes time; not under designer control |
A Hypothetical Illustration
Imagine a fictional wafer on which defects land randomly, roughly one defect per two large dies’ worth of area. A design using one big die per product will lose a substantial portion of dies to those defects. Now imagine the same compute split into four smaller dies, each a quarter of the area. Most small dies are clean, and a defect now wastes only a small die instead of an entire large one. After testing, the good small dies are assembled into packages.
The numbers here are made up to show the mechanism, not to predict real results. The takeaway is that splitting a large die into smaller pieces changes which defects hurt you and how much each one costs.
What This Means If You Buy or Plan Around AI Hardware
Yield is mostly invisible to buyers, but its effects show up in practice.
- Supply can be constrained even when demand is predictable, because production of large, complex chips involves several steps where yield loss compounds. Advanced packaging adds its own capacity limits.
- Product tiers reflect binning. A lower tier may be the same silicon with parts disabled. That does not make it a bad product, but it explains the structure of the lineup.
- Cost trends are not purely about transistor density. Larger, more complex parts can stay expensive even as the process improves.
- Early-life products may behave differently. Newer products on new processes sometimes see supply or pricing shifts as manufacturing matures. Check current vendor and market information instead of assuming.
Frequently Asked Questions
Is yield the same as reliability? No. Yield describes how many dies pass testing at manufacture. Reliability concerns how long those working chips continue to function in the field.
Do manufacturers publish yield numbers? Generally not in detail. Yield is competitively sensitive, so be cautious about any specific figure presented without a clear source.
Why not just make all chips small? Smaller dies yield better, but splitting a design adds communication between dies, which costs latency, energy and complexity. Designers balance both effects.
Does a binned chip perform worse than a full one? It can, depending on what was disabled or limited, but the differences are specified in the product’s documentation. Compare the actual specifications.
Do chiplets eliminate yield problems? They reduce some of them, but introduce packaging yield, where a failure during assembly can waste several good dies. Testing before assembly helps.
Next Step
Take one AI chip you are evaluating and find, in the vendor’s documentation, whether it is a single large die or a multi-die package. Then note how its product tiers differ, so you can tell which differences come from binning and which come from deliberate design.
By SemiChipAI Editorial · Updated November 4, 2026
- chip yield
- die size
- semiconductor defects
- binning